Weidong   Kuang

Associate Professor  

Office: EENGR 3.270
Phone: (956) 665-7133
Email: weidong.kuang@utrgv.edu

Dr. Weidong Kuang





Selected Publications


  • Yu Bai, Bo Hu, Weidong Kuang, and Mingjie Lin. "Ultra-Robust Null Convention Logic Circuit with Emerging Domain Wall Devices," Proceedings of the 26th edition on Great Lakes Symposium on VLSI. 2016: 251–256.

  • Weidong Kuang. "Correction and Comment on “An Adaptive Resolution Asynchronous ADC Architecture for Data Compression in Energy Constrained Sensing Applications”," IEEE Transactions on Circuits and Systems I: Regular Papers 4, no. 60 (2013): 1097–1099.

  • Yu Bai and Weidong Kuang. "Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance," Digital System Design (DSD), 2011 14th Euromicro Conference on. 2011: 247–253.

  • Peiyi Zhao, Jason McNeely, Weidong Kuang, Nan Wang, and Zhongfeng Wang. "Design of sequential elements for low power clocking system," IEEE Transactions on very large scale integration (VLSI) systems 19, no. 5 (2011): 914–918.

  • Weidong Kuang and Yu Bai. "Soft error in FPGA-implemented asynchronous circuits," Programmable Logic (SPL), 2011 VII Southern Conference on. 2011: 221–226.

  • Weidong Kuang, Peiyi Zhao, Jiann Yuan, and Ronald DeMara. "Design of asynchronous circuits for high soft error tolerance in deep submicrometer CMOS circuits," IEEE transactions on very large scale integration (VLSI) systems 18, no. 3 (2010): 410–422.

  • Peiyi Zhao, Jason McNeely, Pradeep Golconda, Soujanya Venigalla, Nan Wang, Magdy Bayoumi, Weidong Kuang, and Luke Downey. "Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems," IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17, no. 9 (2009): 1196–1202.

  • Weidong Kuang, Lizhi Cao, C Yu, and Jiann Yuan. "PMOS breakdown effects on digital circuits–Modeling and analysis," Microelectronics Reliability 48, no. 8 (2008): 1597–1600.

  • Weidong Kuang, Enjun Xiao, Casto Ibarra, and Peiyi Zhao. "Design asynchronous circuits for soft error tolerance," 2007 IEEE International Conference on Integrated Circuit Design and Technology. 2007: 1–5.

  • Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy Bayoumi, Robert Barcenas, and Weidong Kuang. "Low-power clock branch sharing double-edge triggered flip-flop," IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15, no. 3 (2007): 338–345.



Selected Grants and Fellowships


  • Sanjeev Kumar. Developing Remote Laboratory for Improving Engineering Undergraduate Education, UTRGV Internal Seed Research Program (ISRP) Awards, $10,000.00 (January 2017 - December 2017)

  • Weidong Kuang. RET: “Research Experiences for Teachers in Emerging and Novel Engineering Technologies”, NSF(senior personnel), $500,000.00 (2011 - 2015)

  • weidong Kuang. Acquisition of instrumentation for integrated circuit design and device characterization, NSF (PI), $130,000.00 (2008 - 2012)

  • Weidong Kuang. Design asynchronous circuits against particle induced soft error for highly dependable systems, DoD (PI), $180,631.00 (2007 - 2009)

  • Weidong Kuang. Acquisition of instrumentation for security research and training with wireline and wireless information networks, NSF (senior personnel), $280,000.00 (2005 - 2008)



Selected Presentations


  • Weidong Kuang and Edward Banatoski. "Testing for Threshold Logic Circuits Based on Resonant Tunneling Diodes," the 6th IEEE Conference on Nanotechnology, Cincinnati Ohio (July 2006)

Current Courses

CMPE 3343 01I - Prob & Stat Electrical Enginee:
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ELEE 3340 02I - Prob & Stat Electrical Enginee:
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ELEE 3340 01I - Prob & Stat Electrical Enginee:
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CMPE 2130 04 - Digital Systems Engr I Lab:
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ELEE 2130 04 - Digital Systems I Lab:
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CMPE 3403 01 - Electronics for CMPE :
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CMPE 3343 02I - Prob & Stat Electrical Enginee:
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CMPE 3403 A - Electronics for CMPE :
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Previous Courses